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Investigation of Gate Etch Damage at Metal/High- k Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current

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7 Author(s)
Heung-Jae Cho ; Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Younghwan Son ; Byoungchan Oh ; Seunghyun Jang
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Plasma damage on a high-k/SiO2 dielectric at a gate edge during a dry etch process is investigated. The damage was observed to generate slow oxide traps, causing a random telegraph noise (RTN) in a gate edge direct tunneling current. Through the analysis of the RTN, the distribution of the oxide traps in the high-k/SiO2 dielectric was obtained, and the plasma-damage-induced oxide traps were found to be distributed over a wide area of the high-k/SiO2 sidewall at the gate edge region.

Published in:

Electron Device Letters, IEEE  (Volume:32 ,  Issue: 4 )

Date of Publication:

April 2011

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