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This paper reports design and analysis of new low triggering voltage dual-polarity silicon-controlled rectifier (SCR) ESD protection structures and circuits in CMOS. Design optimization technique enables flexible ESD triggering voltage (Vt1), ESD holding voltage (Vh) and ESD protection capability. Measurements show very low and adjustable Vt1, low leakage (Ileak), low noise figure (NF), low ESD-induced parasitic capacitance (CESD) and fast ESD triggering time (t1). It achieves high ESD protection to Si ratio of ESDV~6.83V/ μm2.