Design and analysis of low-voltage silicon-controlled rectifier ESD protection circuit

This paper reports design and analysis of new low triggering voltage dual-polarity silicon-controlled rectifier (SCR) ESD protection structures and circuits in CMOS. Design optimization technique enables flexible ESD triggering voltage (V
_t1
), ESD holding voltage (V
_h
) and ESD protection capability. Measurements show very low and adjustable V
_t1
, low leakage (I
_leak
), low noise figure (NF), low ESD-induced parasitic capacitance (C
_ESD
) and fast ESD triggering time (t
₁
). It achieves high ESD protection to Si ratio of ESDV~6.83V/ μm
²
.