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Frequency multiplier design using BiCMOS-based multiple-peak NDR circuit

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7 Author(s)
Kwang-Jow Gan ; Dept. of Electr. Eng., Nat. Chiayi Univ., Chiayi, Taiwan ; Ping-Feng Wu ; Wu-Yan Shie ; Cher-Shiung Tsai
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We demonstrate a novel frequency multiplier using the negative differential resistance (NDR) circuit based on the standard 0.35 μm BiCMOS technique. This NDR circuit is made of standard Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). We can obtain the three-peak NDR current-voltage (I-V) characteristics by connecting three MOS-HBT-NDR circuits in parallel. These I-V characteristics show high peak-to-valley current ratios with 7.5, 16.8, and 12.1 for three peaks, respectively. Using the folded I-V characteristics, we design a frequency multiplier which can multiply the input saw-tooth signal by a factor of four. The fabrication of this NDR-based frequency multiplier is easier and more convenient compared to the traditional resonant tunneling structure which is implemented by the complicated molecular-beam-epitaxy (MBE) system.

Published in:

Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of

Date of Conference:

15-17 Dec. 2010