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Power-Saving 4 \times 4 Lattice-Reduction Processor for MIMO Detection With Redundancy Checking

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2 Author(s)
Chun-Fu Liao ; Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan ; Yuan-Hao Huang

In this brief, we propose a lattice-reduction (LR) processor for the LR-aided multiple-input-multiple-output detection. The proposed LR processor was developed based on a modified Lenstra-Lenstra-Lovász (LLL) algorithm. We developed a constant-throughput parallel architecture to realize the real-time operation for the LR. The proposed architecture can detect many redundant operations by checking adjacent parallel LLL-reduction results in the previous stage; thereby, the proposed processor can adaptively reduce the processing power for different channel conditions. We designed and implemented the LR processor using the Virtex-4 field-programmable gate array and the United Microelectronics Corporation 90-nm 1P9M complementary metal-oxide-semiconductor technology. The implementation result shows that the proposed LR processor has the highest throughput compared with that of the previously published works. Moreover, the proposed power-reduction technique can reduce the power by an average of 22.42% or a maximum of 26% with negligible performance degradation.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:58 ,  Issue: 2 )