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The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultrascaled FinFET geometries where the presence of a few traps can strongly influence the device behavior. Typical methods for interface trap density (D_it) measurements are not performed on ultimate devices but on custom-designed structures. We present the first set of methods that allow direct estimation of D_it in state-of-the-art FinFETs, addressing a critical industry need.