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A log-based redundant architecture for reliable parallel computation

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3 Author(s)
Sánchez, D. ; Dept. de Ing. y Tecnol. de Comput., Univ. de Murcia, Murcia, Spain ; Aragon, J.L. ; García, J.M.

CMOS scaling exacerbates hardware errors making reliability a big concern for recent and future microarchitecture designs. Mechanisms to provide fault tolerance in architectures must accomplish several objectives such as low performance degradation, power consumption and area overhead. Several studies have been already proposed to provide fault tolerance for parallel codes. However, these proposals are usually implemented over non-realistic environments including the use of shared-buses among processors or modifying highly optimized hardware designs such as caches. Our main design goal is to provide transient fault detection and recovery while modifying hardware as less as possible. To this end, we propose LBRA based on a Hardware Transactional Memory (HTM) architecture in which two redundant threads successfully detects and recovers from transient faults, assuring a consistent view of the memory by means of a pair-shared cacheable virtual memory log which keeps the computation results. Results show that our log-based mechanism introduces a small performance degradation of 5% in a non-faulty scenario. Additionally, we show that LBRA supports huge fault rates such as 100 faults per million of cycles with low additional performance degradation.

Published in:

High Performance Computing (HiPC), 2010 International Conference on

Date of Conference:

19-22 Dec. 2010

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