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This paper presents a novel application mapping strategy onto the mesh topology for Network-on-Chip (NoC) design. Compared to the previously published works, this paper uses the approach of Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the topology using another heuristic algorithm. An iterative improvement phase refines the mapping further. Experimentation with established benchmarks shows that though the static performance of the approach is similar to the best ones previously available, there is 8-17% improvement in latency while considering dynamic communication between the cores.