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A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application

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6 Author(s)
Jungwon Han ; Dept. of Electron. Eng., Ewha Womans Univ., Seoul, South Korea ; Kwisung Yoo ; Dongmyung Lee ; Kangyeop Park
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This paper presents a low-power, gigabit limiting amplifier (LA) for application to optical receivers that employ the negative impedance compensation technique not only to enhance the gain and bandwidth characteristics simultaneously, but also to allow low-voltage, low-power operations. Test chips of the LA were implemented in a standard 0.18-μ m CMOS process, demonstrating 2.5-Gb/s operation with 40-dB gain, 0.053-UI rms jitter for 231-1 pseudorandom bit sequence inputs, 9.5-mVpp input sensitivity for 10-12 bit error rate (BER), and 5.2-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of only 0.25 × 0.1 mm2 . The proposed LA was adopted to realize a low-power, gigabit optical receiver. Fabricated using the same 0.18-μm CMOS technology, the measured results of the optical receiver chip reveal 132.6-dB Ω transimpedance gain, 2.7-GHz bandwidth even with a large 1.5-pF input parasitic capacitance, -16-dBm optical sensitivity for 10-12 BER, and 51-mW power dissipation from a single 1.8-V supply. The area of the whole chip is 1.75 × 0.45 mm2.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 3 )