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A novel array architecture is proposed for floating-gate nor-type nonvolatile memory cells. By embedding a floating n+ region between two cells in each memory pair, punchthrough (PT) immunity is greatly improved. Since the operating cell and the cascade cell belong to two independent word-lines, bit-pattern effect on read and program characteristics is mitigated, and multilevel-cell storage can be easily realized. No additional program disturb has been found. Erase, endurance, and retention characteristics are comparable with its conventional counterpart. According to simulations, Lg as short as 56 nm, which is projected to serve for 28 nm technology node, is feasible without suffering a serious PT effect.