A Compact W-Band CMOS Power Amplifier With Gain Boosting and Short-Circuited Stub Matching for High Power and High Efficiency Operation

Using cascode cell, inductance gain boosting and source degeneration techniques in 90 nm CMOS process, a two-stage power amplifier operating at 80 GHz with a minimum chip area of 0.35 mm
²
demonstrates gain of 18 dB, linear output power of 10.8 dBm, saturated power of 13.3 dBm, and PAE greater than 11.8% when the amplifier is biased at V
_d
= 3 V and V
_g
= 1 V.