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Dynamic gates are preferred in the design of high-performance modules in modern microprocessors due to the relatively high speed of dynamic gates compared with that of standard CMOS gates. These high performance modules have strict timing constraints. Due to the increased process variations in scaled technologies, the dynamic circuit delay exhibits a substantial variability around its nominal value. This delay variability results in violating the timing constraints, and correspondingly, causes a timing yield loss. In this paper, novel negative capacitance circuits are developed, for the first time, to statistically improve the timing yield under process variations. Post layout simulation results, referring to an industrial hardware-calibrated TSMC 65 nm CMOS technology, show that the adoption of the negative capacitance circuit to a 64-input wide dynamic OR gate is capable of improving the timing yield from 50% to 100%. Moreover, the negative capacitance circuit adoption results in reducing the delay variability at the expense of excess power overhead.