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Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

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7 Author(s)
Hamzaoglu, F. ; Portland Technol. Dev., Intel, Hillsboro, OR, USA ; Yih Wang ; Kolar, P. ; Liqiong Wei
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Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes.

Published in:

Design & Test of Computers, IEEE  (Volume:28 ,  Issue: 1 )

Date of Publication:

Jan.-Feb. 2011

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