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Improved evaluation of DRAM transistors and accurate resistance measurement for real chip contacts by nano-probing technique

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5 Author(s)
Hyunho Park ; Semicond. R&D Center, Samsung Electron. Co., Hwasung, South Korea ; Kyosuk Chae ; Yamada, S. ; Hyung-Suk Kuh
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In this study we have measured and analyzed characteristics of real transistors on dynamic random access memories (DRAM) including cell transistor by using nano-probing system for improved failure analysis. Measuring results of the conventional pad probing and nano-probing were compared on test element group (TEG) patterns of large transistors. The transistor characteristics of nano-probing results were evaluated for the each layer of DRAM structure with comparing the TEGs pad probing results. We also have measured sheet resistance (Rs) and contact resistance (Rc) on source and drain of real transistor bit line contacts (BLC) by nano-probing with transmission line model (TLM) method. We could find the effect of floating BLC was negligible and the effective resistance was only depending on the facing length of the contact plug bottom.

Published in:

Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International

Date of Conference:

17-21 Oct. 2010

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