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Investigation into the effect of a “through silicon via”-process on the MOS transistor reliability of a standard 0.13µm CMOS technology

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4 Author(s)
Martin, A. ; Central reliability Dept., Infineon Technol. AG, Neubiberg, Germany ; Borucki, L. ; Reisinger, H. ; Schlunder, C.

Introducing a through-silicon-via (TSV) process into an existing technology node additional degradation mechanisms can be expected. The focus of the investigation was on mechanical stress from the TSV on near by MOS devices and plasma charging effects from the processing of the TSV connected to MOS devices. The significance of these additional effects on the MOS transistor reliability is assessed. It is shown that a TSV-process can introduce severe reliability degradation for MOS transistors.

Published in:

Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International

Date of Conference:

17-21 Oct. 2010