By Topic

High-Performance Partially Depleted SOI PFETs With In Situ Doped SiGe Raised Source/Drain and Implant-Free Extension

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)

We report partially depleted silicon-on-insulator p-channel field-effect transistors fabricated with a 32-nm technology ground rule and featuring SiGe raised source/drain, SiGe channel, and implant-free extension formation process. A respectable drive current of 950 μA/μm is obtained at an OFF current of 100 nA/μm, VDD = 1V, and a contacted gate pitch of 130 nm. Furthermore, when the transistor width is scaled down to 100 nm, the saturation transconductance increases by about 15%, leading to a drive current of 1100 μA/μm.

Published in:

Electron Device Letters, IEEE  (Volume:32 ,  Issue: 3 )