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Development of multi-chip bonding on an integrated packaging platform for silicon photonics

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6 Author(s)
Chee-Wei Tan ; Institute of Microelectronics, A∗STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore, Science Park II, Singapore 117685 ; Qing-Xin Zhang ; Calvin Wei-Liang Teo ; Li-Shiah Lim
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Hybrid integration has been employed for most of the current market available silicon photonics. A novel modular packaging scheme, MEPIC-iMEP3, is proposed for rapid development and high flexibility. One of the critical modules in this packaging scheme is the multichip integration onto the i-MEP3 substrate for sub-micron accuracy. In this study, a series of specially designed test chips and test substrate were fabricated for evaluation using flip-chip bonder. Results show that lateral placement accuracy of <;1μm and rotational accuracy of <;0.05° can be achieved with proper selection of alignment marks. The use of alternating thin Au-Sn layers can precisely control the solder thickness and volume. By optimizing the bonding conditions, a tilting angle of <;0.05° and an average bondline thickness of ~2 μm can be obtained. 3 test chips were bonded onto single substrate successively with a sub-micron accuracy of <;0.5 μm. Shear test is employed to verify the bonding conditions that are properly selected. A simplified MEPIC-iMEP3 test vehicle which requires two bonding for MEPIC and LD was demonstrated with an optical loss of ~-3.0dB due to positional mis-alignment.

Published in:

Photonics Global Conference (PGC), 2010

Date of Conference:

14-16 Dec. 2010