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Algorithm-based fault tolerance on a hypercube multiprocessor

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7 Author(s)
Banerjee, P. ; Dept. of Electr. Eng., Illinois Univ., Urbana, IL, USA ; Rahmeh, J.T. ; Stunkel, C. ; Nair, V.S.
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The design of fault-tolerant hypercube multiprocessor architecture is discussed. The authors propose the detection and location of faulty processors concurrently with the actual execution of parallel applications on the hypercube using a novel scheme of algorithm-based error detection. System-level error detection mechanisms have been implemented for three parallel applications on a 16-processor Intel iPSC hypercube multiprocessor: matrix multiplication, Gaussian elimination, and fast Fourier transform. Schemes for other applications are under development. Extensive studies have been done of error coverage of the system-level error detection schemes in the presence of finite-precision arithmetic, which affects the system-level encodings. Two reconfiguration schemes are proposed that allow the authors to isolate and replace faulty processors with spare processors

Published in:

Computers, IEEE Transactions on  (Volume:39 ,  Issue: 9 )

Date of Publication:

Sep 1990

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