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A 15 MHz to 600 MHz, 20 mW, 0.38 mm ^{2} Split-Control, Fast Coarse Locking Digital DLL in 0.13 \mu m CMOS

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7 Author(s)
Hoyos, S. ; Dept. of Electr. & Comput. Eng., Texas AM Univ., College Station, TX, USA ; Tsang, C.W. ; Vanderhaegen, J. ; Yun Chiu
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A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40×) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 μm × 800 μm in 0.13 μm CMOS.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 3 )

Date of Publication:

March 2012

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