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The turn-on behavior of high-voltage-tolerant nLDMOS SCRs is investigated during CDM ESD events. An early failure occurs because of gate-oxide damage. A device optimization is proposed, which improves the CDM ESD robustness up to 2.7x, unchanging the HBM ESD robustness.
Electron Devices Meeting (IEDM), 2010 IEEE International
Date of Conference: 6-8 Dec. 2010