By Topic

Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-к/metal-gate: Effects of hydrogen thermal annealing and nanowire shape

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hashemi, P. ; Microsyst. Technol. Labs., MIT, Cambridge, MA, USA ; Teherani, J.T. ; Hoyt, J.L.

A detailed study of hole mobility is presented for gate-all-around Si nanowire p-MOSFETs with conformal high-κ/MG and various high-temperature hydrogen annealing processes. Hole mobility enhancement relative to planar SOI devices and universal (100) is observed for 15 nm-diameter circular Si nanowires, due to an optimized anneal process which smoothes and reshapes the suspended nanowires. Increasing hole mobility is experimentally observed with decreasing nanowire width down to 12 nm. The measured inversion capacitance-voltage characteristics are in excellent agreement with quantum mechanical simulations. In addition, a method to extract areal inversion charge density in Si nanowires is introduced and its impact on the mobility of Si nanowires with various shapes is explored.

Published in:

Electron Devices Meeting (IEDM), 2010 IEEE International

Date of Conference:

6-8 Dec. 2010