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Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors

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15 Author(s)
Tachi, K. ; CEA-LETI, MINATEC, Grenoble, France ; Casse, M. ; Barraud, S. ; Dupré, C.
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For the first time, we experimentally analyze the limiting scattering phenomena in gate-all-around nanowire CMOS transistors with aggressive dimensions (Leff of 32 nm for NMOS and 42 nm for PMOS with 15 nm nanowire width) and with high-k/metal gate stacks. One-level and multiple-level stacked nanowire structures are measured and compared. The apparent carrier mobility is degraded in short channel devices. Moreover, we show that the interface quality has a major impact on nanowire transport properties. In rounded nanowires (thanks to H2 anneal), the extracted coulomb-limited mobility decreases whereas the surface roughness-limited mobility increases. Additionally, stacked nanowires suffer from additional coulomb scattering which is attributed to a degraded interface with high-k.

Published in:

Electron Devices Meeting (IEDM), 2010 IEEE International

Date of Conference:

6-8 Dec. 2010