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A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

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33 Author(s)
Chih-Chieh Yeh ; Research & Development, Taiwan Semiconductor Manufacturing Company, No. 8, Li-Hsin 6th Rd., Hsinchu, Taiwan 30077, R.O.C. ; Chih-Sheng Chang ; Hong-Nien Lin ; Wei-Hsiung Tseng
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We show that FinFET, a leading transistor architecture candidate of choice for high performance CPU applications, can also be extended for general purpose SoC applications by proper device optimization. We demonstrate superior, best-in-its-class performance to our knowledge, as well as multi-Vt flexibility for low-operating power (LOP) applications. By high-k/metal-gate (HK/MG) and process flow optimizations, significant drive current (ION) improvement and leakage current (IOFF) reduction have been achieved through equivalent oxide thickness (EOT) scaling and carrier mobility improvement. N-FinFET and P-FinFET achieve, when normalized to Weff (Weff=2xHf+Wf), ION of 1325 μA/μm and 1000 μA/μm at 1 nA/μm leakage current under VDD of 1 V, and 960 uA/um and 690 uA/um at 1 nA/um under Vdd of 0.8V, respectively. This FinFET transistor module is promising for a 32/28nm SoC technology.

Published in:

Electron Devices Meeting (IEDM), 2010 IEEE International

Date of Conference:

6-8 Dec. 2010