Performance benchmarks for Si, III–V, TFET, and carbon nanotube FET - re-thinking the technology assessment methodology for complementary logic applications

Aspiring emerging device technologies (e.g. III–V, CNFET, TFET) are often targeted to outperform Si FETs at the same off-state current (I
off
) and supply voltage (V
dd
). We present a new device technology assessment methodology based on energy-delay optimization which treats I
off
and V
dd
as “free variables”, and bounded by constraints due to device variation and circuit noise margin. We show that for each emerging device (III–V, CNFET, TFET), there is a corresponding and different optimal set of I
off
and V
dd
, and an optimal energy-delay. Today's best-available III–V and CNFET can outperform the best Si FET by 1.5–2x and 2–3.5x, respectively. Projected into the 10nm gate length regime, III–V on-Insulator, CNFET, and TFET are 1.25x, 2–3x, and 5–10x (for FO1 delays of 0.3ns, 0.1ns, and 1ns respectively) better than the ITRS target at the same gate length.