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A 3×3, 5µm pitch, 3-transistor single photon avalanche diode array with integrated 11V bias generation in 90nm CMOS technology

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5 Author(s)
Henderson, R.K. ; Sch. of Eng., Univ. of Edinburgh, Edinburgh, UK ; Webster, E.A.G. ; Walker, R. ; Richardson, J.A.
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A 3×3 prototype image sensor array consisting of 2μm diameter CMOS avalanche photodiodes with 3-transistor NMOS pixel circuitry is integrated in a 90nm CMOS image sensor technology. The 5μm pixel pitch is the smallest achieved to date and is obtained with <;1% crosstalk, 250Hz mean dark count rate (DCR) at 20C, 36% photon detection efficiency at 410nm (PDE) and 107ps FWHM jitter. The small pixel pitch makes it possible to recover the 12.5% fill factor by standard wafer-level microlenses. A 5-stage capacitive charge pump generates the 11V breakdown voltage from a standard 2.5V supply obviating external high voltage generation.

Published in:

Electron Devices Meeting (IEDM), 2010 IEEE International

Date of Conference:

6-8 Dec. 2010