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Ultra-thin chip technology for system-in-foil applications

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9 Author(s)
Angelopoulos, E.A. ; Inst. for Microelectron. Stuttgart (IMS CHIPS), Stuttgart, Germany ; Zimmermann, M. ; Appel, W. ; Endler, S.
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A new additive ultra-thin chip fabrication process is presented, utilizing an array of vertical anchors that mechanically connect silicon membrane chips to a standard silicon wafer. The process is demonstrated down to 8 μm silicon chip thickness, with a chip thickness control better than ±0.2 μm and a surface topography with average roughness <; 7 nm. Such pre-processed wafers can be used for CMOS manufacturing like any conventional silicon substrate. A wide process window with yield figures exceeding 99% is achieved by proper management of the built-in and externally applied stress on the anchors. The excellent mechanical flexibility and stability of these ultra-thin chips make them particularly suitable for system-in-foil applications.

Published in:

Electron Devices Meeting (IEDM), 2010 IEEE International

Date of Conference:

6-8 Dec. 2010