Skip to Main Content
With the continuous shrinking of the feature size, the effect of stress on the performance of the IC device and circuit can no longer be ignored. In fact, stress engineering is becoming more and more widely used today in advanced IC manufacture processes to improve device performance. Different from the intentionally introduced stresses to improve circuit performance, the shallow-trench-isolation (STI) stress, which is exerted by STI wells on the active area of devices, is a by-product of the fabrication process and has increasingly significant impact on the circuit behavior. This paper proposes a complete flow to characterize the influence of STI stress on the performance of RF/analog circuits by considering detailed layout and process information. An accurate and efficient finite-element method-based stress simulator has been developed to extract stress distribution from layouts of IC designs. The existing MOSFET model is also enhanced to capture the effects of stress on mobility, threshold voltage. With the enhanced model, we are able to study the influence of layout-dependent STI stress on the performance of real circuits and establish corresponding optimization strategies. The proposed flow has been applied to a series of RF/analog IC designs based on a 90-nm CMOS technology.