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Most of the off-the-shelf high-speed Serializer-Deserializer (SerDes) chips do not keep the same latency through the data-path after a reset, a loss of lock or a power cycle. This implementation choice is often made because fixed-latency operations require dedicated circuitry and they are usually not needed for most telecom and data-corn applications. However timing synchronization applications and triggers systems of the high energy physics experiments would benefit from fixed-latency links. In this paper, we present a link architecture based on the highspeed SerDeses embedded in Xilinx Virtex 5 and Spartan 6 Field Programmable Gate Arrays (FPGAs). We discuss the latency performance of our architecture and we show how we made it constant and predictable. We also present test results showing the fixed latency of the link and we finally offer some guidelines to exploit our solution with other SerDes devices.
Date of Publication: Feb. 2011