By Topic

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Seon-Kyoo Lee ; Dept. of Electronic and Electrical Engineering, Pohang University of Science and Technology(POSTECH), Pohang, Kyungbuk, Korea ; Seung-Jin Park ; Hong-June Park ; Jae-Yoon Sim

This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 μm CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 μW at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 f J/conversion-step.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:46 ,  Issue: 3 )