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Technological advances driven by the DRAM market demands resulted in thermal challenges arising from increasing power and decreasing space for cooling. This is exacerbated by the packaging of multiple devices within the same footprint based on die stacking or package stacking. In view of the thermal concerns, we conducted a comprehensive thermal study of chip stack and package stack devices at both the component and module level using 3D Computational Fluid Dynamics (CFD) software FLOTHERM. The component level studies are performed under JEDEC standard conditions (JESD 51-2 and JESD 51-6). The simulation results were used to obtain thermal resistance matrixes and the Linear Superposition (LSP) principle was applied to estimate the temperature rise and thermal cross talk for several power split configurations. It was found that under the investigated conditions, there is an optimum power split configuration that will result in the smallest junction temperatures even when the same total package power is applied and the value of this power is influenced by the package structure. As the key application of DRAM chip stack and package stack is for high density module, studies were performed for both chip stack and package stack devices on high density memory modules under server application environments. Under the module level environment, when the top die is active with DDR3 power application, both the dual chip stack and package stack are able to achieve maximum junction temperatures less than 85°C when wind speed of 4m/s is applied, without the need for external heat spreader. To optimize the thermal performance of the investigated devices, the effects of various design variations were also studied. The addition of solder balls under the die area was found to improve the thermal performance of the investigated dual stack packages. The impact of increased stacking was evaluated where the thermal performance of quad stack devices were compared to the dual stack d- - evices. The quad stack and dual stack devices exhibited similar thermal behaviors, where the chip stack devices showed minor temperature differences within the chip stack, while the temperature differences between the different dies are larger in the package stack devices. Valuable insights on the package structure, design and thermal performance at both component and module level thus obtained are presented.
Date of Conference: 8-10 Dec. 2010