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Efficient Design and Performance Analysis for AMBA Bus Architecture Based System-on-Chip

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3 Author(s)
Anurag Shrivastavastava ; Dept of Electron. & Comm., Priyatam Inst. of Technol. & Manage., Indore, India ; G. S. Tomar ; Kamal K. Kalra

This paper describes a System-on-Chip platform architecture for low power high performance Digital Signal Processing intensive applications. The platform is based on the AMBA SoC bus protocol and incorporates a novel interfacing scheme which utilizes the bus hierarchy within AMBA in order to allow single and multiple high performance DSP Intellectual Property cores to be integrated to the SoC platform. The paper describes the overall SoC platform architecture and the integration scheme, providing results for area usage and power consumption of the main blocks in the platform with an example of a three DSP core integration case.

Published in:

Computational Intelligence and Communication Networks (CICN), 2010 International Conference on

Date of Conference:

26-28 Nov. 2010