Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Efficient Design and Performance Analysis for AMBA Bus Architecture Based System-on-Chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shrivastavastava, A. ; Dept of Electron. & Comm., Priyatam Inst. of Technol. & Manage., Indore, India ; Tomar, G.S. ; Kalra, K.K.

This paper describes a System-on-Chip platform architecture for low power high performance Digital Signal Processing intensive applications. The platform is based on the AMBA SoC bus protocol and incorporates a novel interfacing scheme which utilizes the bus hierarchy within AMBA in order to allow single and multiple high performance DSP Intellectual Property cores to be integrated to the SoC platform. The paper describes the overall SoC platform architecture and the integration scheme, providing results for area usage and power consumption of the main blocks in the platform with an example of a three DSP core integration case.

Published in:

Computational Intelligence and Communication Networks (CICN), 2010 International Conference on

Date of Conference:

26-28 Nov. 2010