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Performance Verification for Cache Memory of Multicore Processor

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3 Author(s)
Dhakad, P. ; Dept. of Electron. & Commun. Eng., Mandsaur Inst. of Technol., Mandsaur, Malaysia ; Katariya, A. ; Arya, A.

The cache hierarchy design in existing SMT and a superscalar processor is optimized for latency, but not for bandwidth. The size of the Level 1 (L1) data cache did not scale over the Past decade. Instead, larger unified Level 2 (L2) and Level 3 (L3) caches were introduced. The present paper is the part of the L3 cache. This paper describes last level cache memory decoding structure, which is designed mainly to improve performance. Functional verification as well as pre layout and post layout STA and ERC verifications are done on the 4MB cache. Results of each verification flow are presented. Based on the SDP methodology, good placement and routing, RC extraction, and noise analysis are achieved. SDP methodology is proven better than the RLS methodology for data path configurations. Cadence tools are used for performing the verification of SDP flows.

Published in:

Computational Intelligence and Communication Networks (CICN), 2010 International Conference on

Date of Conference:

26-28 Nov. 2010