By Topic

Short-Channel Performance Improvement by Raised Source/Drain Extensions With Thin Spacers in Trigate Silicon Nanowire MOSFETs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Masumi Saitoh ; Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama, Japan ; Yukio Nakabayashi ; Ken Uchida ; Toshinori Numata

We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width (WNW) down to 10 nm. We found that the parasitic resistance (RSD) of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance (Cpara) increases by spacer thinning, Cpara increase is much smaller than RSD reduction, and great performance improvement is obtained for a WNW of less than 15 nm.

Published in:

IEEE Electron Device Letters  (Volume:32 ,  Issue: 3 )