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Fully integrated linear single photon avalanche diode (SPAD) array with parallel readout circuit in a standard 180 nm CMOS process

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4 Author(s)
Isaak, S. ; Dept. of Electr. & Electron. Eng., Univesrity of Nottingham, Nottingham, UK ; Bull, S. ; Pitter, M.C. ; Harrison, I.

This paper reports on the development of a SPAD device and its subsequent use in an actively quenched single photon counting imaging system. The device was fabricated in a UMC 0.18 μm CMOS process. The device has a cross-section of circular p+/n-well pn junction SPAD with 10 μm diameter active area. A low-doped p-guard ring (t-well layer) encircles the active area to prevent the premature reverse breakdown on a reverse biased diode breakdown.

Published in:

Enabling Science and Nanotechnology (ESciNano), 2010 International Conference on

Date of Conference:

1-3 Dec. 2010

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