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A comparative study on ASIC design of high frequency low power photoreceiver using 0.15µm CMOS technology

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3 Author(s)
Mausumi Maitra ; Department of Information Technology, Government College of Engineering and Ceramic Technology, West Bengal University of Technology, Kolkata-700010, India ; Kaushik Chakraborty ; Shubhajit Roy Chowdhury

The current work focuses on the design of a fully integrated single beam photoreceiver that can accept optical pulses of 850 nm wavelength at a bandwidth as high as 1 Gbps. This is highly suitable for implementation in fiber optic LANs and short haul optical interconnects. The recent advances of fiber optic communication technology with VLSI circuit design methodologies has motivated the development of low power complementary metal oxide semiconductor (CMOS) photoreceiver capable of detecting optical pulses at 1 Gbps. The receiver integrates a photo-detector and a preamplifier circuit. The idea of using the CMOS technology is to achieve a high frequency low power implementation of the system. The average power dissipation of the receiver has been found earlier to be less than 0.105 mW at a supply voltage of 1 V for 0.3 μm CMOS technology. The current work has been done using the 0.15 μm CMOS technology with power dissipation as low as. Also, a comparative study of frequency response of the receiver circuit has been made for different values of junction resistance and capacitance of the p-i-n photodiode. The whole work has been done using TSPICE simulation tool.

Published in:

Electrical and Computer Engineering (ICECE), 2010 International Conference on

Date of Conference:

18-20 Dec. 2010