By Topic

Dual stack method: A novel approach to low leakage and speed power product VLSI design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Islam, M.S. ; Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh ; Nasrin, M.S. ; Mansur, N. ; Tasneem, N.

The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality on a chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Today leakage power has become an increasingly important issue in processor hardware and software design. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. In this paper, we propose a new dual stack approach for reducing both leakage and dynamic powers. Moreover, the novel dual stack approach shows the least speed power product when compared to the existing methods.

Published in:

Electrical and Computer Engineering (ICECE), 2010 International Conference on

Date of Conference:

18-20 Dec. 2010