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Analysis of performance and implementation complexity of simplified algorithms for decoding Low-Density Parity-Check codes

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2 Author(s)
Chandrasetty, V.A. ; Sch. of Electr. & Inf. Eng., Univ. of South Australia, Mawson Lakes, SA, Australia ; Aziz, S.M.

This paper presents a novel technique to significantly reduce the implementation complexity of Low-Density Parity-Check (LDPC) decoders. The proposed technique uses high precision soft messages at the variable nodes but scales down the extrinsic message length, which reduces the number of interconnections between variable and check nodes. It also simplifies the check node operation. The effect on performance and complexity of the decoders due to such simplification is analyzed. A prototype model of the proposed decoders compliant with the WiMax application standard has been implemented and tested on Xilinx Virtex 5 FPGA. The implementation results show that the proposed decoders can achieve significant reduction in hardware complexity with comparable decoding performance to that of Min-Sum algorithm based decoders. The proposed decoders are estimated to achieve an average throughput in the range of 6-11 Gbps, even with short code lengths.

Published in:

GLOBECOM Workshops (GC Wkshps), 2010 IEEE

Date of Conference:

6-10 Dec. 2010