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As CPU performance has continually enhanced by transistor scaling, the demand in DRAM performance has been also increased. To meet the performance requirement, 3D chip stacking using Through-Silicon-Via (TSV) has been developed in recent years. For TSV technology, devices are connected by short vertical through-wafer via and thus enhance the performance such as high density, low power and high bandwidth. As transistor scaling becomes more difficult, TSV offer the promising solution for further performance enhancement. TSV formation, wafer thinning, microbump fabrication and chip stacking are key processes for 3D chip stacking using TSV. In this paper, the process steps of TSV formation are examined and discussed. On the other hand, since chip strength of thinned wafer is significantly decreased, the impact of wafer thinning on DRAM devices performance is also presented. After TSV formation, the fine pitch microbumps are fabricated for chip connection. At last, the 5-strata C2W stacking using Cu filled TSV and Sn-Ag/Cu microbump is achieved.