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In Today's competitive and rapidly changing electronics market, the speed and effectiveness of product testing have a significant impact on time-to-market. You need to make Design-For-Testability (DFT) an essential part of your design process, along with the need for a reliable method of knowing the test coverage and how to improve it. This paper describes the modified Boundary-Scan Register (BSR) Cell, described in IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture, to facilitate the detection of additional manufacturing defects in BSR Cell by adding a small test logic, which will become a part of original BSR Cell. The basic idea is to increase the stuck-at fault coverage of BSR cell by including the update-register (latched parallel output) Flip-Flop in BSR chain and once the update-register is being included in the chain; we can target more manufacturing defects to cover during BSR chain-test. This increases the fault-coverage of the BSR Pad Ring and will also help validation engineers to ease out their debugging efforts on board level with added quality to the delivered chips to customer. This BSR cell design modification can be extended to any of the BC type cell structure, compliant to IEEE Standard 1149.1 Boundary-Scan Architecture.