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The paper proposes the idea of implementing a general multi-bit error correcting code (ECC) based on Orthogonal Latin Square (OLS) Codes in on-chip hardware, but then selectively, on a chip-by-chip basis, using only a subset of the code's check bits (subset of the rows in its H-matrix) depending on the defect map for a particular chip. The defect map is obtained from a memory characterization test which identifies which cells are defective or marginal. The idea proposed here is that if a general t-bit error correcting code is implemented in hardware and requires cfull=n-k check bits for k information bits, then once the defect map is known, the defective cells become erasures w.r.t. the ECC. This fact can be used to select only a subset of the n-k rows in the H-matrix which are sufficient to provide the desired error detection/correction capability in the presences of the known erasures. By selectively reducing the number of rows in the H-matrix, the number of check bits that are actually stored and used, cused, can be restricted and the corresponding unused ECC hardware disabled. This reduces the check bit storage requirements and hence frees up more of the cache for storing data and improving performance. This strategy is applied to the problem of providing reliable cache operation in ultra-low voltage modes, and results indicate that with the proposed post-manufacturing ECC customization, a fraction of the number of check bits are required compared to using a full OLS code for handling a particular defect rate.