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We present a high precision Time-to-Digital Converter (TDC) architecture suitable for multi-channel implementations such as in monolithic arrays of single-photon avalanche diode (SPAD) detectors for time-correlated single photon counting (TCSPC) and LIDAR applications. The proposed architecture is based on a `coarse' counter and two-stage interpolators, thus reaching a high interpolation factor with moderate chip area consumption. A prototype chip has been fabricated in a 0.35 μm standard CMOS technology and contains smart-pixels with the TDC and the 20 μm diameter SPAD detector with its analog sensing and quenching electronics. The 250 μm × 250 μm smart-pixel reaches a resolution of 10 ps and a dynamic range of 160 ns. It is suitable for imaging arrays aimed at photon timing applications like FLIM, FCS, FRET, but also Time-Of-Flight applications like LIDAR.