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Multiplier circuits play an important role in reversible computation, which is helpful in diverse areas such as low power CMOS design, optical computing, DNA computing and bioinformatics. We have proposed a reversible multiplier circuit design in NCT gate library which is based on generating all partial products in one step and then summing their partial products using binary tree network. The proposed reversible multiplier design has two components which are reversible partial product generation circuit and reversible parallel adder circuit. Our design has minimum number of garbage bits, gate count, and quantum cost. We have shown that the HNG, TSG and MKG gates proposed for designing of a component of multiplier circuit (full adder) is neither unique nor special and many such gates may be proposed which can also perform all boolean operations. As an example three such new gates have been presented here.
Date of Conference: 19-21 Nov. 2010