Skip to Main Content
Median filter is a non-linear filter used in image processing for impulse noise removal during morphological operations, image enhancement and other image processing operations. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. Real-time applications, such as video and high speed acquisition cameras often require fast algorithms for processing. Reconfigurable hardware filters can be embedded with image acquisition system to achieve this goal. In this paper we propose a hardware implementation of a median filter with programmable window sizes ranging from 3×3 to 7×7. This median filter was designed, simulated and synthesized on the Xilinx family of FPGAs (XC3S500E of Spartan-3E). The performance of the same was evaluated for variety of images. For 3×3 window size, the maximum operating frequency achieved was approximately 89 MHz and for 5×5 window sizes, the maximum operating frequency achieved was approximately 89 MHz. The VHDL was used to design the above 2-D median filter using ISE (Xilinx) tool. The proposed hardware implementation took on an average 0.00246 m sec. For a frame of size 4×4 (for window size 3×3), 0.22472 m sec on for a frame of size 16×16 (for window size 5×5) and 0.468 m sec on a average for a frame of size 16×16 (for window size 7×7). The algorithm proposed for the median filter is based on sorting pixel samples and extracting their median values.