We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Improved reachability analysis of large finite state machines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Cabodi, G. ; Dipartimento di Autom. e Inf., Politecnico di Torino, Italy ; Camurati, P. ; Quer, S.

BDD-based symbolic traversals are the state-of-the-art technique for reachability analysis of finite state machines. They are currently limited to medium-small circuits for two reasons: peak BDD size during image computation and BDD explosion for representing state sets. Starting from these limits, this paper presents can optimized traversal technique particularly oriented to the exact exploration of the state space of large machines. This is possible thanks to: temporary simplification of a finite state machine by removing some of its state elements; and a "divide-and-conquer" approach based on state set decomposition. An effective use of secondary memory allows us to store relevant portions of BDDs and to regularize access to memory, resulting in less page faults. Experimental results show that this approach is particularly effective on the larger ISCAS'89 and ISCAS'89-addendum'93 circuits.

Published in:

Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on

Date of Conference:

10-14 Nov. 1996