By Topic

A hardware/software co-design architecture for packet classification

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ahmed, O. ; Sch. of Eng., Univ. of Guelph, Guelph, ON, Canada ; Chattha, K. ; Areibi, S.

Packet Classification involves matching information from a packet's header to a set of rules in a database in order to determine the manner in which the packet should be processed by network processors. The PCIU algorithm is a novel classification algorithm which improves upon previously published techniques in the literature. The main features of the PCIU algorithm are the low pre-processing time and capability of incremental rule update. Using the network processor to implement packet classification would cause saturation even when the best performing packet classification algorithm is used. In this work, we propose a hardware implementation of the PCIU algorithm. Results obtained indicate that the hardware/software co-design approach achieves 4.3x speedup in terms of preprocessing over a pure software implementation and 5.3x speedup for classification.

Published in:

Microelectronics (ICM), 2010 International Conference on

Date of Conference:

19-22 Dec. 2010