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Cell phones and pocket PCs have burst-mode type integrated circuits, which for the majority of the time are in an idle state. For such circuits, it is acceptable to have leakage during the active mode. However, during the idle state it is extremely wasteful to have leakage, as power is unnecessarily consumed with no useful work being done. In this paper, we proposed a novel leakage reduction technique useful in reduction of leakage currents in active & standby mode and then compare and contrast it with other well established leakages currents reduction techniques. A high threshold connecting transistor is used to reduce leakage effects in complementary CMOS transistors of inverter. To maintain the performance of inverter an auxiliary NMOS is configured as a sleep transistor with PDN. Experiments conducted on a proposed inverters using 0.18 μm TSMC® using TANNER EDA tool. Results obtained shows significant reduction in leakage power and delay when compared to other techniques.