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Pipelined architecture for discrete wavelet transform implementation on FPGA

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2 Author(s)
Bahoura, M. ; Dept. of Eng., Univ. of Quebec at Rimouski, Rimouski, QC, Canada ; Ezzaidi, H.

In this paper, we propose a pipelined real-time architecture for forward/inverse wavelet transforms that take into account the filter group delays. The required resources and the reconstruction error of this architecture were evaluated and compared to those of the conventional one. These architectures were implemented on FPGA using Xilinx System Generator and XUP Virtex-II Pro development board.

Published in:

Microelectronics (ICM), 2010 International Conference on

Date of Conference:

19-22 Dec. 2010