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In this paper, we propose a Design Space Exploration (DSE) methodology to produce multi-core system architectures with optimal scheduling, number of cores, number of buses and hardware-software partitioning from Task Precedence Graphs (TPGs). The viability and potential of the proposed methodology is demonstrated by extensive experimental results to conclude that it is an efficient scheme to obtain the optimality with hard and large task graph problems.
Microelectronics (ICM), 2010 International Conference on
Date of Conference: 19-22 Dec. 2010