Referenced Items are not available for this document.
In this paper, we propose a Design Space Exploration (DSE) methodology to produce multi-core system architectures with optimal scheduling, number of cores, number of buses and hardware-software partitioning from Task Precedence Graphs (TPGs). The viability and potential of the proposed methodology is demonstrated by extensive experimental results to conclude that it is an efficient scheme to obtain the optimality with hard and large task graph problems.
Published in:
Microelectronics (ICM), 2010 International Conference on
Date of Conference: 19-22 Dec. 2010
- Page(s):
- 260 - 263
- Print ISBN:
- 978-1-61284-149-6
- INSPEC Accession Number:
- 11763762
- Conference Location :
- Cairo
- Digital Object Identifier :
- 10.1109/ICM.2010.5696133
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
