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Parallel and distributed solutions are gaining increasing importance in designing embedded systems. Future parallel embedded systems are expected to have several hundred processing cores, improving the performance/power ratio. Multilevel caches in a multicore architecture require huge amount of power and may decrease processing speed due to cache's dynamic behavior. In this work, we investigate the impact of a Miss Table and victim caches at the cache level on performance and power consumption. The Miss Table holds information about the memory blocks those might cause more level-1 cache misses. Victim caches hold level-1 victim blocks. Cache locking algorithm and cache replacement scheme can directly be benefited by using the information stored in Miss Table and victim caches. We simulate a quad-core system with a two-level cache memory subsystem under MPEG4, H.264/AVC, FFT, and MI workloads. Experimental results show that the addition of the Miss Table and victim caches reduces the mean delay per task and the total power consumption by 32% and 41%, respectively.