By Topic

MOS current mode logic realization of digital arithmetic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
El-Hariry, Y.M. ; Electr. & Electron. Eng. Dept., German Univ. in Cairo (GUC), New Cairo, Egypt ; Madian, A.H.

In this paper, MOS current mode logic (MCML) and dynamic current mode logic (DyCML) techniques are analyzed and applied to the generation of digital arithmetic circuits. A full adder structure is demonstrated, analyzed and compared with equivalent CMOS, Domino and CPL structures and realized using 0.18 μm CMOS technology operating with 1.5 V and -1.5 V supply voltages. Also, a four bit multiplier and a CORDIC block were analyzed and realized using MOS Current Mode Logic. PSPICE simulation results of each realization have been demonstrated.

Published in:

Microelectronics (ICM), 2010 International Conference on

Date of Conference:

19-22 Dec. 2010