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Using Partial Reconfiguration in an Embedded Message-Passing System

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4 Author(s)
Saldana, M. ; ArchES Comput., Toronto, ON, Canada ; Patel, A. ; Hao Jun Liu ; Chow, P.

Partial Reconfiguration (PR) is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of it continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard to use feature. In this paper, the new Partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to allow hardware designers to create template bit streams, which are pre-designed, pre-routed, generic bit streams that other users can reuse for many applications. Our goal is to provide a simplified, reusable, high-level and portable PR interface for X86-FPGA hybrid machines. PR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by preliminary PR overhead measurements.

Published in:

Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on

Date of Conference:

13-15 Dec. 2010